Microsoft Excel Data Analysis - Learn How The Experts Use It
Vincent Gomez
5.0 (5,696)·2h 57m · 40 lectures
$3.00$12–$199up to −98%
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VLSI Synthesis and Constraints part1
Realization on paper, RTL, Manual netlist generation, STA, Constraints, Tcl Scripting, Synthesizing using OpenRoad Tool
5.06 reviews57 learners
- All Levels
- 12h 47m video
- 47 lectures
- English
- Captions
- Updated 2026
Taught by Budumuru Vijay Kumar
- 12h 47m of on-demand video
- 47 lectures across 10 sections
- One-off payment — no subscription
- Lifetime access on web and mobile
- Closed captions (English)
Curriculum
10 sections47 lectures12h 47m total
- Introduction14:57
- Installation of Ubuntu and OpenRoad in your laptop0:01
- Lab Material0:06
- Lab to build expression w(x+y+z)+xyz realize on paper10:05
- Lab to build expression w(x+y+z)+xyz using Nand gates8:22
- lab_a behav rtl and manual netlist collecting lib cells8:45
- lab_a manual netlist build18:09
- lab_a openroad23:59
- OpenRoad Tcl Basic Commands-Part124:58
- OpenRoad Tcl Basic Commands-Part226:03
- OpenRoad Tcl Basic Commands-Part314:27
- OpenRoad Tcl Basic Commands-Part420:09
- OpenRoad Tcl Basic Commands-Part522:30
- Lab_b Realize on Paper7:42
- Lab_b Behav rtl9:38
- Lab_b Manual netlist part115:33
- Lab_b Manual netlist part222:18
- Lab_b implement using OpenRoad33:10
- Lab_c Realization on paper Part18:58
- Lab_c Realization on paper Part212:28
- Lab_c RTL and Manual netlist38:05
- Lab_c Implementation using OpenRoad26:37
- Lab_d Realization on paper16:28
- Lab_d Behav RTL22:31
- Lab_d Manual netlist part130:03
- Lab_d Manual netlist part225:06
- Lab_d Implementation using OpenRoad Part120:01
- Lab_d Implementation using OpenRoad Part210:16
About this course
7 Hands on labs a. Using Nand gates for a given expression w(x+y+z)+xyz b. Construct 16 X 1 multiplexer with Two 8 X 1 and one 2 X 1 multiplexers. c. 3-bit Comparator d. Synchronous and asynchronous flop e. latch (Normal D Latch, Reset Latch (active-low async reset) and Set Latch (active-high async set) f. Design with posedge and negedge flops. Analyze timing paths for all combinations g. Sequence detector Each lab contains Concept realization on paper RTL development Creating handwritten / custom netlis…
Before you start
- Programming: Unix Gvim Awk Python
- VLSI syntaxes ( Library Sdc Def Lef)
- Basic Digital Electronics ( Boolean algebra Gate level minimization Combinational and sequential logic Registers and counters)
Who it’s for
- Beginner Physical design engineers who wants to build high frequency designs like 5Ghz at 2nm nodes
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