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VLSI/FPGA Design P1: CMOS Gates & Arithmetic Datapath
Design skyscrapers from bricks
5.09 reviews117 learners
- Beginner
- 5h 49m video
- 19 lectures
- English
- Captions
- Updated 2025
Taught by SKY SiliconThink
- 5h 49m of on-demand video
- 19 lectures across 4 sections
- One-off payment — no subscription
- Lifetime access on web and mobile
- Closed captions (English)
Curriculum
4 sections19 lectures5h 49m total
- Introduction of the whole course(all parts)6:40
- Glossary44:02
- Conventions2:21
- Silicon and Diode4:54
- nMOS & pMOS Transistor12:08
- Switch Level Model and Inverter34:50
- PVT Corners and Quiz10:15
- Correction of explain for figure of PVT corner3:57
- Basic Logic Gates20:47
- Tranmition Gate and Tristate20:27
- Factors Affect Cell Delay4:42
- Latch & DFF and Deep Understanding for Setup/Hold Time1:00:16
- Extra 1: Why no D2Q Delay for DFF2:36
- Extra 2: Multi-Driven is not Allowed2:12
- Extra 3: All the Factors That Affect Cell Delay2:13
- Architecture for Adder & Subtractor and Use the Ideal behind the Arch.1:02:23
- Architecture for Multiplier and Divider34:42
- Arithmetic of Real Number and Any Math. Function17:26
- Promotion: VLSI/FPGA Design Resume Project: 2D DMA Controller with APB+AXI Inf.2:19
About this course
Please contact SKY (DM or E-mail to siliconthink@126.com) for special offer of $12.99 USD. This chapter is foundation of design SOC and FPGA, that's bricks of skyscrapers. Contents in chapter 1: 1: Behavior and characteristics of CMOS gate: switch model, transition time, delay time, PVT corner. 2: Using CMOS gate to build basic logic function gates: NAND, NOR, XOR, mUX. 3: Build arithmetic datapth using basic logic gates: adder, subtractor, multiplier and divider. Learning the HW architecture ideas behind them,…
Before you start
- Basic knowledge of digital fundamental
- Basic C or C++ programing language
Who it’s for
- Senior undergraduate students of EE or higher
- IC design/verification engineers with 0~2 years’ experience
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